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WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protec-
tion. The AT25080B/160B is divided into four array segments. One-quarter, one-half, or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read only. The block
write protection levels and corresponding status register control bits are shown in Table 3-4 .
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regu-
lar memory cells (e.g., WREN, t WC , RDSR).
Table 4-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
0
1(1/4)
2(1/2)
3(All)
BP1
0
0
1
1
BP0
0
1
0
1
AT25080B
None
0300 ? 03FF
0200 ? 03FF
0000 ? 03FF
AT25160B
None
0600 ? 07FF
0400 ? 07FF
0000 ? 07FF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit
is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0”. When the device
is hardware write protected, writes to the status register, including the block protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory that
are not block-protected.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long as the WP pin is held low.
Table 4-5.
WPEN Operation
Protected
Unprotected
Status
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
Protected
Writeable
Protected
Writeable
Protected
Writeable
Register
Protected
Writeable
Protected
Protected
Protected
Writeable
READ SEQUENCE (READ): Reading the AT25080B/160B via the Serial Output (SO) pin requires the following
sequence. After the CS line is pulled low to select a device, the read op-code is transmitted via the SI line followed
by the byte address to be read (A15 – A0, see Table 3-6 ). Upon completion, any data on the SI line will be ignored.
The data (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest address is reached, the
address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read
cycle.
8
AT25080B/160B
5228E–SEEPR–3/12
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